1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly, to a semiconductor device having a well structure for improving element isolation characteristics by preventing interference between adjacent wells.
2. Description of the Background Art
In recent years, miniaturization and larger scale integration are required for semiconductor devices such as DRAMs (Dynamic Random Access Memory) resulting in the employment of a well structure where wells of different conductivity types are formed in an adjacent manner. Such a well structure had a problem that soft errors of DRAMs and latch up of CMOSs (Complementary Metal Oxide Semiconductor) occurred due to interference between adjacent wells. Development in various well structures has been proceeded to prevent interference between such wells.
In "IEDM 88" pp. 48-51, for example, a semiconductor device having a well structure for preventing soft errors of a SRAM (Static Random Access Memory) is disclosed. The wells disclosed in this document are all formed by thermal diffusion steps. In these days of high integration density, it has become difficult to control the impurity concentration distribution of wells by thermal diffusion.
A conventional technique to prevent interference between adjacent wells is known, where a semiconductor device has an impurity layer of high concentration formed beneath an isolation oxide film separating wells from each other at the semiconductor substrate surface.
A conventional semiconductor device will be explained hereinafter with reference to FIG. 14, which has a well structure for preventing interference between adjacent wells. In the well structure of FIG. 14, an n well 2, a p well 3, and an n well 4 are allocated adjacent to each other at respective depths from the surface of a p type silicon substrate 1. Each well is separated by an isolation oxide film 6 at the surface of silicon substrate 1. A p well 5 is formed inside n well 4. For the purpose of improving the isolation characteristic between the wells, an n type layer 7 of high concentration, a p type layer 8 of high concentration, an n type layer 9, and a p type layer 10 of high concentration are formed in n well 2, p well 3, n well 4, and p well 5, respectively, beneath the isolation oxide film.
The manufacturing steps of the above-mentioned semiconductor device having a conventional well structure will be described hereinafter with reference to FIGS. 15-26.
A resist film 11 is formed on the main surface of p type silicon substrate 1 to have an opening only at the region where n well 4 is to be formed. Phosphorus which is impurity of n type is implanted at a predetermined implantation energy and dosage (FIG. 15) to form n well 4 (FIG. 16).
A resist film 12 is then formed having an opening at the region where n well 2 is to be formed. Phosphorus is implanted at an implantation energy that is lower than that used for forming n well 4 (FIG. 17) to result in well 2 (FIG. 18).
Next, resist film 13 is formed having an opening only at the region where p wells 3 and 5 are to be formed. Boron which is an impurity of p type is implanted (FIG. 19) to form p wells 3 and 5 (FIG. 20).
Oxide film 14 and silicon nitride film (Si.sub.3 N.sub.4 film) 15 are formed all over the main surface of semiconductor substrate 1 (FIG. 21). Silicon nitride film 15 is patterned by photolithography and etching (FIG. 22). Then, resist film 16 is formed to cover the surface of n wells 2 and 4. Boron is implanted (FIG. 23) to form p type layers 8 and 10 of high concentration partially at the surface of p wells 3 and 5.
Resist film 16 is removed, and resist film 17 is formed to cover the surface of p wells 3 and 5 (FIG. 24). Phosphorus is implanted to form n type layers 7 and 9 of high concentration at the surface of n wells 2 and 4, respectively. Then, resist film 17 is removed (FIG. 25).
Isolation oxide film 6 is formed by thermal oxidation to result in the structure shown in FIGS. 26 and 14.
The above-described conventional well structure and manufacturing method had the following problems.
High concentration n type layer 7 and high concentration p type layers 8 and 10 right beneath isolation oxide film 6 are formed prior to the isolation oxide film 6 formation step for element isolation enhancement. Impurities of high concentration n type layer 7 or high concentration p type layers 8 and 10 will spread out into the active regions of each well at the time of thermal diffusion due to the high temperature of the thermal treatment for forming isolation oxide film 6. If the channel width of the transistor formed in these active regions is small, the threshold voltage V.sub.th will become too high to yield the disadvantage that the transistor does not operate properly, due to the high concentration of impurities in the active region. This was a great disadvantage in the miniaturization of the device for increasing storage capacity. This disadvantageous phenomenon is called "narrow channel effect".
The conventional well structure shown in FIG. 14 also had the following problem. It can be appreciated from FIG. 27A that semiconductor substrate 1 and n well 4, and n well 4 and p well 5 are respectively isolated from each other by pn junctions, with a junction capacitance of C.sub.1 and C.sub.2 at each pn junction. This means that although these pn junctions are separated regarding the direct current component of current, electrical connection is established regarding alternating-current component. Therefore, if n well 4 has supply voltage Vcc applied with a high frequency noise V.sub.N (t), the high frequency noise V.sub.N (t) will appear as the difference between potential V.sub.5 of p well 5 and potential V.sub.1 of semiconductor substrate 1. In the conventional well structure of FIG. 27A, the p type impurity concentration of semiconductor substrate 1 right beneath n well 4 is relatively low so that a depletion layer is easily generated in the semiconductor substrate 1 side at the pn junction formed by n well 4 and semiconductor substrate 1. This reduces junction capacitance C.sub.1, whereby most of the high frequency noise V.sub.N (t) results in a fluctuation of potential V.sub.5 of p well 5. This induced the problems that information stored in the memory formed on p well 5 was lost and the operation of other elements were unstable.